1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory (hereinafter referred to as EPROM, erasable programmable read only memory), and more specifically to an EPROM in which data can be easily erased.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a structure of a conventional UV-EPROM (Ultra-Violet EPROM).
Referring to the figure, a X address decoder 52 and a Y gate sense amplifier 53 for selecting rows and columns of memory cells are connected to a memory cell matrix 51 comprising a plurality of memory transistors (which will be described later) arranged in rows and columns. A Y address decoder 54 which supplies column selecting information is connected to the Y gate sense amplifier 53 and the X address decoder 52 and the Y address decoder 54 are respectively connected to an address buffer 55 in which address information is temporarily stored. An input-output buffer 57 which temporarily stores input-output data is connected to the Y gate sense amplifier 53. The address buffer 55 and the input-output buffer 57 are connected to a control logic 56 which controls the operation of the EPROM. The control logic 56 controls in accordance with a chip enable signal CE an output enable signal OE and a program signal PGM
FIG. 2 is a perspective view showing schematic structure of the memory cell matrix 51 shown in FIG. 1.
In the figure, a plurality of word lines WL.sub.1, WL.sub.2. . . WL.sub.i are arranged in the row direction and a plurality of bit lines BL.sub.1, BL.sub.2, . . . BL.sub.i are arranged in the column direction so as to intersect the word lines orthogonally, thereby forming a matrix. Memory transistors Q.sub.11, Q.sub.12, . . . Q.sub.ii each having a floating gate are arranged at respective intersections of the word lines and the bit lines. The memory transistor has its drain connected to each bit line, its control gate connected to each word line and its source connected to each of ground lines (S.sub.1, S.sub.2 . . . ). As is shown in the figure, the sources of the memory transistors belonging to the same row are connected to each other and to the ground lines (S.sub.1, S.sub.2 . . . ,) arranged on both sides.
FIG. 3 is a plan view showing a portion of the definite structure of a conventional memory cell matrix and FIGS. 4 and 5 are cross sectional views taken along the lines IV--IV and V--V of FIG. 3, respectively.
Referring to FIGS. 3 to 5, the structure of the memory cell will be described. An N.sup.+ impurity region 3 which will be the drain region of the memory transistor and N.sup.+ impurity regions 2a and 2b which will be the source regions are formed on a main surface of a semiconductor substrate 1. Floating gates 5a and 5b are formed on channel regions which are sandwiched by the N.sup.+ impurity regions 3, 2a and 2b with a first gate oxide film 4 interposed therebetween. The first gate oxide film 20 is sandwiched by a thick isolating oxide film 19 formed on the main surface of the semiconductor substrate 1 whereby the active region thereof is defined. Control gates 6a and 6b formed of polycide are formed on the floating gates 5a and 5b with a second gate oxide film 22 interposed therebetween, the control gates 6a and 6b of respective transistors are tied to each other in the row direction to form a word line 6. An interlayer insulating film is formed on the entire surface of the main surface of the semiconductor substrate 1 to cover the word line 6. Contact holes 12 to provide contact between the impurity regions 2a and 2b and the bit lines are provided on the interlayer insulating film 4. Bit lines 7 formed of aluminum wiring are formed in the column direction on the entire insulating film 4. Impurity regions 2a and 2b which will be the source regions are connected with each other and extend in the row direction and are connected to the source lines 17 extending in the column direction through the contact holes 13. Although not shown in the figure, normally one source line (S.sub.1, S.sub.2 . . . ) 17 is provided for every sixteen bit lines 7.
The writing operation to the memory transistors in the EPROM structured as above will be briefly described referring to FIGS. 1 to 6.
Address signals A.sub.O to A.sub.i which will be X address signals (word line selecting signals) and Y address signals (bit line selecting signals) are time sequentially inputted to the address buffer 55 and these signals are applied to the Y gate sense amplifier 53 through the X address decoder 52 and the Y address decoder 54, respectively. Consequently, one word line and one bit line are selected and a high voltage V.sub.pp (about 12.5 V in the case of 1 M bit degree of integration) is applied thereto. On this occasion, the non-selected word lines and all source lines are brought to the ground level and the non-selected bit lines BL are brought to the floating state.
Consequently, a high voltage V.sub.pp is applied to the control gate and the drain region of the memory transistor to which the selected word lines and bit lines are connected, and, since the potential of the source region is at the ground level, a relatively large current flows to the channel of the transistor. Therefore, hot electrons are implanted to the gate oxide film near the drain region 3 and to the floating gates 5a and 5b due to the electric field in the oxide film. As a result, electrons are stored in the floating gates 5a and 5b, causing increase of the threshold voltage of the transistor. Thus, the writing is carried out. The electrons stored in the floating gates 5a and 5b are maintained even after the application of the high voltage V.sub.pp since the surroundings of the floating gates 5a and 5b are covered with the insulating film.
FIG. 6 is a graph showing a current voltage characteristic of a memory transistor in the erased and written states. The written and erased states are defined by the presence absence of the electrons in the floating gates of the transistor as described above. As is shown in the figure, the threshold voltage of the memory transistor at the written state (storing "0") is different from that in the erased state (storing "1"). Therefore, non-volatile information can be obtained by setting the intermediate value as a reading gate voltage V.sub.R. More specifically, at the reading gate voltage V.sub.R shown in the figure, the memory transistor in the written state becomes non-conductive, so that no current flows to the bit line. Meanwhile, the memory transistor in the erased state becomes conductive, so that current flows to the bit line.
Next, the reading operation of the memory transistor of the EPROM will be briefly described with reference, to FIGS. 1 to 5.
In the similar manner as the above described writing operation, address signals A.sub.O to A.sub.i which will be the X address signals and Y address signals are time sequentially inputted to the address buffer 5 and one word line and one bit line are selected. Let us consider a case in which a word line WL.sub.2 and a bit line BL.sub.2 are selected, for example. In this case, the presence absence of information in the memory transistor Q.sub.22 is read. A voltage V.sub.R is applied to the word line WL.sub.2 while a prescribed voltage is applied to the bit line BL.sub.2. Other non-selected word lines and all source lines are brought to the ground level and other non-selected bit lines are brought to the floating state. Consequently, a prescribed voltage is applied to the drain region of the transistor Q.sub.22, and, since the source region is at the ground potential, a drain current flows between the source and drain regions if the transistor Q.sub.22 is in the erased state. This means that a current flows to the bit line BL.sub.2. Meanwhile, if the transistor Q.sub.22 is in the written state, it is difficult for a current to flow between the source and drain regions, that is, the bit line BL.sub.2. The amount of current flow in the selected bit line BL.sub.2 brings a change of voltage applied to the bit line BL.sub.2, and this change is detected and amplified by the Y gate sense amplifier 53 using the reference voltage as a reference. The reading operation is carried out by taking out the detected and amplified voltage signal through the input/output buffer 57 as information.
Description will be given of a case in which the stored data is erased. The erasure of the stored data is to bring all memory transistors to the state of "0" again by discharging electrons from the floating gates of the memory transistors storing electrons. The erasure of the stored data is carried out by irradiating ultraviolet rays (UV) on the surface of an IC chip to discharge electrons from all floating gates to the conduction band of the semiconductor substrate by light excitation. Therefore, the EPROM is usually contained in a package 9 having a window 10 for irradiating ultraviolet rays as shown in FIG. 7.
As described above, since a conventional EPROM should be irradiated by ultraviolet rays in erasing data, a window must be provided on the package. In addition, a special glass is used for the window, so that the package is more expensive than a package of for example an EEPROM in which the data can be erased without using ultraviolet rays. Therefore, it increases the cost of the EPROM.
FIG. 8 is a schematic cross sectional view of an EEPROM in which the erasure of information is carried out electrically. Referring to FIG. 8, a conventional EEPROM has a similar structure as the EPROM shown in FIG. 5. More specifically, the EEPROM comprises a floating gate formed on a main surface of a P type semiconductor substrate 1 for storing charges representing information, a control gate 6 for applying-potential to the floating gate, an N type impurity region, not shown, and erasing gates 14a and 14b for erasing charges stored in the floating gate. In the EEPROM, the writing is carried out in the similar manner as the writing of EPROM. In erasing, a high voltage is applied to the erasing gates 14a and 14b and the electrons stored in the floating gate are discharged to the erasing gates due to the tunnel phenomenon through tunneling insulating layers 15a and 15b.
However, the tunneling insulating films and the erasing gates should be provided independently from the essential components. Therefore, the area per 1 bit memory cell becomes larger, increasing the size of the chip.